Skip to content

Changes

Summary

  1. Add Cache Line Writeback Instruction (commit: 19993ce) (details)
  2. Add CLWB to X86 support_features_test (commit: 2c3ffab) (details)
Commit 19993ceda65a5cf5039ec8783af8f38c51d48a67 by James You
Add Cache Line Writeback Instruction

This commit adds the clwb instruction motivated
by the writeback0 intrinsic available in the Unsafe Java library.

The intrinsic permits users to write back a cache line
if cache line writeback is enabled by the underlying VM.
This instruction maps 1-1 with the intrinsic method.

The CPUID feature flag OMR_FEATURE_X86_CLWB is already implemented and
should be used to check whether the instruction is supported in the
underlying hardware. To use this instruction, the caller should check if
said feature flag is enabled for the cpu.

Signed-off-by: James You <james.you@protonmail.com>
(commit: 19993ce)
The file was modified fvtest/compilerunittest/x/BinaryEncoder.cpp (diff)
The file was modified compiler/x/codegen/X86Ops.ins (diff)
The file was modified compiler/x/env/OMRCPU.cpp (diff)
Commit 2c3ffab8c50a38a66c013908585414124873b6ad by James You
Add CLWB to X86 support_features_test
(commit: 2c3ffab)
The file was modified compiler/env/ProcessorInfo.hpp (diff)
The file was modified compiler/x/env/OMRCPU.cpp (diff)
The file was modified compiler/x/codegen/OMRCodeGenerator.hpp (diff)